Pipelined ADCs have been used extensively (for example) in high performance digital communication systems, waveform acquisitions, and instrumentations. While the speed of state-of-the-art pipelined ADC has exceeded 100 MSPS, the resolution is generally limited by the inter-stage gain error and/or DAC gain error resulting from circuit nonidealities (i.e., capacitor mismatch and finite opamp gain, and so forth). Thus, most pipelined ADCs with more than 12-bit resolution usually require some linearity enhancement techniques.
There also exists an architecture, known as a “split ADC” architecture, that can be used to perform background calibrations, and, turning to FIG. 1, an example of a convention ADC 100 using a split ADC architecture can be seen. This ADC 100 generally comprises channels or ADCs 102-1 and 102-2, adders 104-1 and 104-2, and a divider 106. Typically, ADCs 102-1 and 102-2 have the same general structure, and, in operation, receive the same analog input signal AIN so as to perform a data conversion at approximately the same time (generating digital output signals DA and DB, respectively). The difference ΔD between these output signals DA and DB, which is generated by adder 104-2 (which operates as a subtractor), can be used for calibrating ADCs 102-1 and 102-2, while an average of the output signals DA and DB (generated by adder 104-1 and divider 106) would correspond to a digital output for ADC 100. However, there are difficulties in compensating for inter-stage gain errors and/or DAC gain errors when ADCs 102-1 and 102-2 are pipelined ADCs.
Therefore, there is a need for a method and/or apparatus that compensates for inter-stage gain error and/or DAC gain error in a pipelined ADC.
Some examples of conventional circuits are: Park et al., “A 10-b 100MS/s CMOS pipelined ADC with 1.8V power supply,” Proc. ISSCC Digest Technical Papers, pp. 130-131, February 2001; McNeill et al., “Split ADC Architecture for Deterministic Digital Background Calibration of a 16-bit 1-MS/s ADC,” IEEE Journal of Solid State Circuits, vol. 40, pp. 2437-2445, December 2005; Li et al., “Background calibration techniques for multistage pipelined ADCs with digital redundancy,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 9, pp. 531-538, September 2003; U.S. Pat. Nos. 6,081,215; 6,445,317 6,452,518; 7,312,734; and U.S. Patent No. 2006/0176197.